<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Yash Kumar | UCSC OSPO</title><link>https://deploy-preview-1007--ucsc-ospo.netlify.app/author/yash-kumar/</link><atom:link href="https://deploy-preview-1007--ucsc-ospo.netlify.app/author/yash-kumar/index.xml" rel="self" type="application/rss+xml"/><description>Yash Kumar</description><generator>Wowchemy (https://wowchemy.com)</generator><language>en-us</language><image><url>https://deploy-preview-1007--ucsc-ospo.netlify.app/author/yash-kumar/avatar_hu0e41d72690f2f76f938a22fec610c272_516310_270x270_fill_q75_lanczos_center.jpg</url><title>Yash Kumar</title><link>https://deploy-preview-1007--ucsc-ospo.netlify.app/author/yash-kumar/</link></image><item><title>Memory Compiler in OpenROAD</title><link>https://deploy-preview-1007--ucsc-ospo.netlify.app/report/osre24/ucsc/openroad/20240613-yashkumar3066/</link><pubDate>Thu, 13 Jun 2024 00:00:00 +0000</pubDate><guid>https://deploy-preview-1007--ucsc-ospo.netlify.app/report/osre24/ucsc/openroad/20240613-yashkumar3066/</guid><description>&lt;p>Greetings! I&amp;rsquo;m Yash Kumar working on the &lt;a href="project/osre24/openroad/openroad/">OpenROAD Memory Compiler Project&lt;/a> for which my &lt;a href="https://docs.google.com/document/d/1EGxLSYzVWMtBHmT6m3QQTBA_rqJnMB9qfqR51GSb71k/edit?usp=sharing" target="_blank" rel="noopener">proposal&lt;/a> under the mentorship of &lt;a href="https://deploy-preview-1007--ucsc-ospo.netlify.app/author/matt-liberty/">Matt&lt;/a> and &lt;a href="https://deploy-preview-1007--ucsc-ospo.netlify.app/author/austin-rovinski/">Austin&lt;/a> aims to enhance the OpenROAD flow by integrating a DFFRAM generator that extensively uses the OpenDB database to build and layout various memory components like bits, bytes, and 32x32 configurations and more. Taking inspiration from the work of the &lt;a href="https://github.com/AUCOHL/DFFRAM" target="_blank" rel="noopener">AUCOHL repository’s DFFRAM memory compiler&lt;/a>,&lt;/p>
&lt;p>The goal is to develop a DFF/Latch-based RAM that utilizes standard cell libraries. The compiler will generate different views (HDL netlist, functional models, LEF, DEF, Timing, etc.) for specified size configurations, targeting compact design and optimal routing. The compiler should work across various PDKs satrting with Sky130. My initial works tries to test the Bit and Byte level design.&lt;/p></description></item></channel></rss>